This application is based on Japanese Patent Application No. 2002-145284, filed on May 20, 2002, the entire contents of which are incorporated herein by reference.
A) Field of the Invention
The present invention relates to a semiconductor device and more particularly to a semiconductor device having multilevel wiring layers.
B) Description of the Related Art
As semiconductor integrated circuit devices are highly integrated, the wiring scale of each device increases one generation after another. According to the road map, the total wiring length of a typical semiconductor chip in the 0.18 xcexcm generation of 1999 was about 500 m and the number of wiring layers was three or four. The total wiring length of a typical semiconductor chip in the 0.10 xcexcm next generation will be about 4 km and the number of wiring layers will be about ten. The total wiring length of a typical semiconductor chip of the 0.05 xcexcm generation in about ten years may be over 200 km.
Both high integration and high speed of semiconductor integrated circuits are desired. For the high speed operation, it is desired to lower the wiring resistance and the parasitic capacitance. In order to lower the wiring resistance, aluminum (Al) wiring has been replaced with copper (Cu) wiring. It is difficult to use wiring material having a resistivity lower than Cu. When reduction of the wiring resistance reaches near its limit, it becomes necessary to lower the parasitic capacitance of wiring in order to realize high speed operation.
The parasitic capacitance of wiring is dependent on the dielectric constant of insulating layers dielectrically separating the wiring. Fluorine-doped silicon (FSG having a dielectric constant ∈ of about 3.7) is used in place of undoped silicon oxide (USG), phosphorous doped silicon oxide (PSG), boron and phosphorous doped silicon oxide (BPSG) respectively having a dielectric constant ∈ of about 4.1. Organic insulating material having a much lower dielectric constant (registered trademarks SiLK, FLARE and the like) is also used. Porous material (such as porous silicon oxide) realizing a further lowered dielectric constant has been proposed.
FIGS. 8A, 8B and 8C show examples of a wiring structure according to prior art.
FIG. 8A shows an example of a wiring layer in the 0.18 xcexcm generation. Between a first wiring layer M1 and a third wiring layer M3, a second wiring layer M2 buried in a silicon oxide layer 100 is disposed. For example, the line width of the second wiring layer M2 is 260 nm and the height thereof is 545 nm. The distance between the first and second wiring layers M1 and M2 is, for example, about 750 nm. The sheet resistance of the wiring layer M2 is 91 mxcexa9/xe2x96xa1, and the parasitic capacitance is 253 fF/mm (0.137 fF/grid). The dielectric constant ∈ of the silicon oxide layer 100 is about 4.1.
FIG. 8B shows an example of a wiring layer in the 0.13 xcexcm generation. Between a first wiring layer M1 and a third wiring layer M3, a second wiring layer M2 is disposed. Insulating films burying the second wiring layer M2 include an insulating layer 101a of silicon oxide under the second wiring layer, an organic insulating layer 101b having a dielectric constant of about 2.7 and laterally separating the main regions of the second wiring layer, and an insulating layer 101c of silicon oxide disposed on the organic insulating layer. For example, the line width of the second wiring layer M2 is about 200 nm and the height thereof is about 275 nm. The distance between the first and second wiring layers M1 and M2 is, for example, about 350 nm. The sheet resistance of the wiring layer M2 is about 90 mxcexa9/xe2x96xa1, and the parasitic capacitance is about 214 fF/mm (0.086 fF/grid).
FIG. 8C shows an example of a wiring layer in the 0.1 xcexcm generation. Between a first wiring layer M1 and a third wiring layer M3, a second wiring layer M2 is disposed. The second wiring layer M2 is buried in an organic insulating layer 102 having a low dielectric constant of about 2.7. For example, the line width of the second wiring layer M2 is about 140 nm and the height thereof is about 250 nm. The distance between the first and second wiring layers M1 and M2 is, for example, about 300 nm. The sheet resistance of the wiring layer M2 is about 95 mxcexa9/xe2x96xa1, and the parasitic capacitance is about 185 fF/mm (0.052 fF/grid).
The parasitic capacitance of wiring can be lowered by using insulating material having a low dielectric constant. However, the line width of a wiring layer in a semiconductor integrated circuit device becomes wider and the height thereof becomes higher in the upper level wiring layer.
The main role of lower level wiring lines is transistor signal lines and the like, and the pitch of wiring lines is small. The smaller the parasitic capacitance of wiring lines is, the better it is for high speed operation. To this end, low dielectric constant insulating material such as an organic film is used.
The main role of upper level wiring lines is power supply lines. High speed operation is not required but heat radiation and workability have a priority over the high speed operation. These requirements can be met and high reliability can be realized by using insulating films made of mainly silicon oxide which has been widely used conventionally. By using different insulating materials for upper and lower wiring lines, a high performance of semiconductor integrated circuit devices can be expected.
A variety of makers have proposed low dielectric constant films such as organic films and inorganic films. These low dielectric constant materials have physical constants very different from those of insulating material made of mainly silicon oxide.
If insulating layers having very different physical constants are laminated, cracks or peeling is likely to be formed between the layers.
An object of this invention is to provide a semiconductor device having multilevel wiring layers with a high performance and a high reliability.
Another object of the invention is to provide a semiconductor device capable of relaxing stress in a multilevel wiring layer structure.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a number of semiconductor elements formed on the semiconductor substrate; a plurality of lower level wiring layers electrically connected to the semiconductor elements; a plurality of first insulating layers electrically separating the lower level wiring layers and having a first dielectric constant; a plurality of middle level wiring layers electrically connected to the lower level wiring layers; a plurality of second insulating layers electrically separating the middle level wiring layers and having a second dielectric constant larger than the first dielectric constant; a plurality of upper level wiring layers electrically connected to the middle level wiring layers; a plurality of third insulating layers electrically separating the upper level wiring layers and having a third dielectric constant larger than the second dielectric constant.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a number of semiconductor elements formed on the semiconductor substrate; a plurality of lower level wiring layers electrically connected to the semiconductor elements; a plurality of middle level wiring layers electrically connected to the lower level wiring layers; a plurality of upper level wiring layers electrically connected to the middle level wiring layers; a plurality of first insulating layers electrically separating the lower level wiring layers and having a first physical constant; a plurality of third insulating layers electrically separating the upper level wiring layers and having a third physical constant different from the first physical constant; a plurality of second insulating layers electrically separating the middle level wiring layers and having a second physical constant having an intermediate value between the first and third physical constants.
With these configurations, the reliability of a semiconductor device having multilevel wiring layers can be improved while the performance thereof is maintained high.